CV
Tasneem Mazhar
Summary
Adjunct Lecturer at BRAC University and MSc student in Applied Mathematics and Computational Sciences at North South University. Researcher in semiconductors, phase change memory, and computational device modeling.
Education
- Applied Mathematics and Computational SciencesNorth South University
- Electrical and Electronic Engineering2023North South UniversityGPA: 3.93/4.00
- A Levels2019AcademiaCourses: Chemistry, Biology, Physics, Mathematics
- O Levels2017Academia
Work Experience
- Adjunct Lecturer2024-05Teaching CSE250, CSE251, CSE350; developing course content and lab assessments.
- Lab Coordinator2025-02Coordinating CSE350L lab curriculum for OBE and BAETE standards.
- Research Assistant2023-12 - 2024-12Performed DFT/MD simulations and FEM modeling of PCM nanodevices.
- Lab Instructor2024-02 - 2024-06Conducted labs in Circuits I, Digital Logic, and Control Engineering.
- Undergraduate Teaching Assistant2022-10 - 2024-01Assisted in Electromagnetics, Semiconductor Devices, and Engineering Economics.
Skills
Simulation Tools
- Quantum ESPRESSO
- COMSOL
- CST
- Multisim
- LTSpice
- Proteus
- Logisim
Programming
- Python
- C
- Linux Scripting
Data Analysis
- MATLAB
- OriginPro
- GNUPlot
- Excel
Design and Documentation
- AutoCAD
- SketchUp
- LaTeX
- MS PowerPoint
Soft Skills
- Technical Writing
- Research
- Time Management
- Problem Solving
Publications
- Effects of Cell Aspect Ratio and Applied Pulse Parameters on Resistance Drift in Ge2Sb2Te5 PCM Nanodevices20242024 IEEE Nanotechnology Materials and Devices Conference (NMDC)This paper explores how cell geometry and pulse parameters influence resistance drift in PCM nanodevices using GST-225.
Teaching
- CSE250, CSE251, CSE3502024BRAC University, CSE DepartmentRole: Adjunct Lecturer
- Circuits I, Digital Logic, Control Engineering Labs2024North South UniversityRole: Lab Instructor
- Electromagnetic Fields, Semiconductor Devices, Engineering Economics2022North South UniversityRole: Undergraduate Teaching Assistant
Portfolio
- Ab-initio Simulation of GST Phases
- Synchronized Memory Counter
Interests
- Semiconductors and Nanoelectronics
- First-Principles Calculations (DFT/MD)
- Phase Change Memory and Emerging Devices
- FEM and Device Simulation